I meant more of the whole approach of designing chips with efficiency as a top priority which means they get the best performance they can within their efficiency targets, which is always more optimal than users tinkering on their own. Efficiency and performance are kind of different sides of the same coin.
I meant more of the whole approach of designing chips with efficiency as a top priority which means they get the best performance they can within their efficiency targets, which is always more optimal than users tinkering on their own. Efficiency and performance are kind of different sides of the same coin.