What are CPU designs which are not fetch/store but operate directly on RAM?
I only know about the design of the Nintendo Entertainment System (NES), where the CPU does not have registers (AFAIK) and operates directly on RAM, with fast access to low addresses in the RAM.
What CPUs/Systems do you know, which also do not do fetch/store for their operands? Which systems are out there? Why do CPUs like RISC/Arm/AMD64 use fetch/store, what are the tradeoffs? Are there different architectures for CPUs working on operands outside of fetch/store, DMA and stack machines?
As far as I know the 6502 clone in the NES has 3 general-purpose registers: X, Y and accumulator. Many of the instructions operate on them.
https://www.masswerk.at/6502/6502_instruction_set.html
It’s a good question though. I am just not aware of a mainstream CPU architecture without registers.
Thank you very much for your answer! :-)
I would also assume, that at least 1-3 registers are ‘always’ in a CPU, like instruction pointer, top of stack for stack machines or for modern CPUs frame pointers.
For the NES, as far as I understand, you can also operate on the lower memory addresses with the CPU by simply referring to their address.
In the end, what triggered my question is the (banal) insight, that one actually does not need registers from computer science point of view and I am wondering if there are any implementations.
(Obviously for speed reasons alone one wants registers…)
Interesting question, a lot of CPUs have instructions that act directly on memory, but not having any registers would be a weird kind of system. You could design one for yourself en run it on an FPGA, but it probably wouldn’t work very well. At the very least you would want to have an instruction pointer and accumulation registers.
Just to be more specific, from your link the operations with operands from low registers “zpg zeropage OPC $LL operand is zeropage address (hi-byte is zero, address = $00LL)” looks like exactly the stuff I am interested in. It seems to me, that they are like 256 (slower) pseudo registers.
Ah, I see what you mean now. Yeah I’m guessing there are code sequences where it’s more efficient (either in clocks or code size or simple convenience) to operate on these 256 low addresses than repeating load/hit/store.